Multidimensional fields of data processing cells are already known. The generic class of these modules includes in particular systolic arrays, neural networks, multiprocessor systems, processors having a plurality of arithmetic units and/or logic cells and/or communicative/peripheral cells (IO), interconnection and network modules such as crossbar switches as well as known modules of the generic types FPGA, DPGA, Chameleon, XPUTER, etc. In particular there are known modules in which first cells are reconfigurable during run time without interfering with the operation of other cells (see, for example, German Patent No. 44 16 881, German Patent Application Nos. DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53, and DE 199 80 312.9, International Application No. PCT/DE 00/01869, German Patent Application Nos. DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, and DE 101 11 014.6, International Application No. PCT/EP 00/10516, and European Application No. EP 01 102 674.7). These are herewith incorporated fully into the present text for disclosure purposes. Reference is also made to the Chameleon system processor architecture. However, the usability of the structure mentioned last for data processing purposes is more comparable to an arrangement described in German Patent Application No. DE 101 03 624.
The data processing cells of these modules may now execute different functions such as Boolean and/or arithmetic operations on input operands. Connections running between the cells are also adjustable and typically include buses capable of interconnecting in various ways and thus creating a multidimensional field whose interconnection is adjustable. The cells exchange information such as status signals, triggers or the data to be processed over the buses or other lines. The cells are typically arranged in rows and columns in a two-dimensional processor field, with the outputs of cells of a first row being connected to buses to which the inputs of cells of the next row are also to be connected. In a conventional design (Pact XPP), forward and backward registers are also provided for carrying data while bypassing cells on bus systems of other rows, achieving a balance of branches to be executed simultaneously, etc. There have already been proposals for providing such forward and/or backward registers with a functionality that goes beyond pure data transfer.
In general, however, it is necessary to define which cell performs which data processing steps, where this cell is situated and how it is connected. In the related art, strategies for automatic control of placement mechanisms and routing mechanisms are already known.
Placers, for example, typically operate according to a force method, which uses forces between cells for optimum placement of dependent cells by simulating connections by springs in a physical model. This usually yields a mostly suitable placement result.
In addition, German Patent No. 44 16 881, and German Patent Application Nos. DE 196 54 846.2-53 and DE 102 06 653.1 describe data processing methods for reconfigurable modules in which data is read out of one or more memories in each processing step and is then processed and written to one or more memories. According to the related art, the read and write memories are placed differently and are typically placed in opposition (FIGS. xxua, xxub, xxuc and German Patent Application No. DE 102 06 653.1, FIG. 3).
Special reconfiguration methods (wave reconfiguration) are also described in German Patent Application Nos. DE 197 04 728.9, DE 199 26 538.0, DE 100 28 397.7 for the aforementioned modules, thus permitting particularly efficient reconfiguration by jointly transmitting the reconfiguration information together with the last data to be processed via the data buses and/or trigger buses, and by reconfiguring the buses and cells immediately after successful processing.
To perform a certain type of data processing, each cell must be assigned a certain function and at the same time a suitable position in space and interconnection must be provided. Therefore, before the multidimensional processor field processes data as desired, it is necessary to ascertain which cell is to execute which function; a function must be defined for each cell involved in a data processing task, and the interconnection must be determined.